View HYB18L512160BF-75_3319294.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

december 2006 hyb18l512160bf-7.5 hye18l512160bf-7.5 drams for mobile applications 512-mbit mobile-ram rohs compliant data sheet rev. 1.22
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com data sheet. hy[b/e]18l512160bf-7.5 512-mbit mobile-ram qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 01132005-06iu-igvm hyb18l512160bf-7.5, hye18l512160bf-7.5 revision history: 2006-12, rev. 1.22 page subjects (major changes since last revision) all qimonda update previous version: 2005-11, rev. 1.11 51 idd7 change from 20 to 25 54 updated the package drawing. previous revision: rev. 1.1 50 table 20: delete note 6 change note 6 from (tt -1 ) to [0.5 x (tt -1)] . 51 - idd4: change from 60 to 90 - idd7: change from 40 to 20 - add a note: value shown is typical 54 - updated the package drawing. all - package name: change from p-tfbga to pg-tfbga - remove all references to hyb18l512160bc-7.5 and hye18l512160bc-7.5 previous version: rev. 1.0
data sheet. rev. 1.22, 2006-12 3 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 1overview 1.1 features ? 4 banks 8 mbit 16 organization ? fully synchronous to positive clock edge ? four internal banks for concurrent operation ? programmable cas latency: 2, 3 ? programmable burst length: 1, 2, 4, 8 or full page ? programmable wrap sequence: sequential or interleaved ? programmable drive strength ? auto refresh and self refresh modes ? 8192 refresh cycles / 64 ms ? auto precharge ? commercial (0 c to +70 c) and extended (-25 c to +85 c) operating temperature range ? dual-die 54-ball pg-tfbga package (12.0 8.0 1.2 mm) ? rohs compliant products 1) power saving features ? low supply voltages: v dd = 1.70 v to 1.95 v, v ddq = 1.70 v to 1.95 v ? optimized self refresh ( i dd6 ) and standby currents ( i dd2 / i dd3 ) ? programmable partial array self refresh (pasr) ? temperature compensated self-refresh (tcs r), controlled by on-chip temperature sensor ? power-down and deep power down modes table 1 performance 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. part number speed code - 7.5 unit speed grade 133 mhz access time ( t acmax ) cl = 3 6.0 ns cl = 2 7.0 ns clock cycle time ( t ckmin ) cl = 3 7.5 ns cl = 2 9.5 ns
data sheet. rev. 1.22, 2006-12 4 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 2 memory addressing scheme table 3 ordering information item addresses banks ba0, ba1 rows a0 - a12 columns a0 - a9 type 1) 1) hy[b/e]: designator for memory products (hyb: standard temp range, hye: extended temp. range) 18l: 1.8 v mobile-ram 512: 512 mbit density 160: 16 bit interface width b: die revision f: green product -7.5: speed grade(s): min. clock cycle time package description standard temperature range hyb18l512160bf-7.5 pg-tfbga-54 133 mhz 4 banks 8 mbit 16 lp-sdram extended temperature range hye18l512160bf-7.5 pg-tfbga-54 133 mhz 4 banks 8 mbit 16 lp-sdram
data sheet. rev. 1.22, 2006-12 5 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 1.2 pin configuration figure 1 standard ballout 512-mbit mobile-ram 1.3 description the hy[b/e]18l512160bf is a high-speed cmos, dynamic random-access memory contai ning 536,870,912 bits. it is internally configured as a quad-bank dram. the hy[b/e]18l512160bf achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clo ck. read and write accesses are bu rst-oriented. accesses start at a selected location and continue for a programmed number of lo cations (1, 2, 4, 8 or full page) in a programmed sequence. the device operation is fully synchronous: all inpu ts are registered at the positive edge of clk. the hy[b/e]18l512160bf is specially designed for mobile ap plications. it operates from a 1.8 v power supply. power consumption in self refresh mode is dras tically reduced by an on-chip temperature sensor (octs); it can further be reduced by using the programmable part ial array self refresh (pasr). a conventional data-retaining power down (pd) mode is avai lable as well as a non-data-retaining deep power down (dpd) mode. the hy[b/e]18l512160bf is housed in a dual-die 54-ball pg-tfbga package. it is available in commercial (0 c to +70 c) and extended (-25 c to +85 c) temperature ranges. 6 3 3 1 5 $ 1 - 6 $ $ 1 $ 1 $ 1 $ 1 6 3 3 1 6 $ $ 1 # + % # , + ! ! ! ! $ 1 $ 1 $ 1 6 3 3 " ! $ 1 $ 1 $ 1 6 $ $ , $ 1 - $ 1 6 3 3 1 6 $ $ 1 6 3 3 1 " ! ! ! ! 0 6 $ $ 6 $ $ 1 $ 1 $ 1 $ 1 $ 1 ! " # $ & ' ( * % # ! 3 2 ! 3 7 % ! ! 6 3 3 ! 6 $ $ ! ! ! $ 1 ! 6 3 3 . # $ 1 # 3
data sheet. rev. 1.22, 2006-12 6 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 2 functional block diagram # + % # , + # 3 2 ! 3 # ! 3 7 % ! d d r e s s 2 e g i s t e r 2 o w ! d d r e s s - u x 2 e f r e s h # o u n t e r # o m m a n d $ e c o d e - o d e 2 e g i s t e r s # o n t r o l , o g i c " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k # o l u m n , o g i c # o l u m n ! d d r e s s # o u n t e r , a t c h " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r ) / ' a t i n g $ 1 - - a s k , o g i c # o l u m n $ e c o d e r ! ! " ! " ! $ 1 $ 1 $ a t a / u t p u t 2 e g $ a t a ) n p u t 2 e g , $ 1 - 5 $ 1 - " a n k " a n k " a n k
data sheet. rev. 1.22, 2006-12 7 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 1.4 pin definition and description table 4 pin description ball type detailed function clk input clock: all inputs are sampled on the positive edge of clk. cke input clock enable: cke high activates and cke low deactivates internal clock signals, device input buffers and output drivers. taking cke low provides: ? precharge power-down and self re fresh operation (all banks idle) ? active power-down (row active in any bank) ? suspend (access in progress). input buffers, excluding clk and cke are disabled during power-down. input buffers, excluding cke are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on syst ems with multiple memory banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dq0 - dq15 i/o data inputs/output: bi-directional data bus (16 bit) ldqm, udqm input input/output mask: input mask signal for write cycles and output enable for read cycles. ? for writes, dqm acts as a data mask when high. ? for reads, dqm acts as an output enable and pl aces the output buffers in high-z state when high (two clocks latency). ? ldqm corresponds to the data on dq0 - dq7; udqm to the data on dq8 - dq15. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an activate, read, write or precharge command is being applied to. ba0, ba1 also determine which mode register will be loaded during a mode register set command (mrs or emrs). a0 - a12 input address inputs: a0 - a12 define the row address during an active command cycle. a0 - a9 define the column address during a read or write command cycle. in addition, a10 (= ap) controls the auto precharge operation at the end of the burst read or write cycle. during a precharge command, a10 (= ap), in conjunction with ba0, ba1 , control which bank(s) will be precharged: ? if a10 is high, all four banks will be prec harged regardless of the state of ba0 and ba1 ? if a10 is low, ba0, ba1 define the bank to be precharged. during mode register set commands, the address inputs hold the opcode to be loaded. v ddq supply i/o power supply: isolated power for dq output buffers for improved noise immunity: v ddq = 1.70 v to 1.95 v v ssq supply i/o ground v dd supply power supply: power for the core logic and input buffers, v dd = 1.70 v to 1.95 v v ss supply ground n.c. ? no connect
data sheet. rev. 1.22, 2006-12 8 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2 functional description read and write accesses to the mobile-ram are burst orient ed. accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed: ? ba0, ba1 select the banks ? a0 - a12 select the row the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the mobile-ram must be initialized. the following subsections provide detailed information covering device initialization, register definition, co mmand description, and device operation. 2.1 power on and initialization the mobile-ram must be powered up and in itialized in a predefined manner (see figure 3 ). operational proc edures other than those specified may result in undefined operation. figure 3 power-up sequence and mode register sets power-up: vdd and ck stable load mode register load ext. mode register = don't care ba0=l ba1=h t rfc t rfc t mrd t mrd t rp 200s t ck all banks dq (high-z) dqm ba0,ba1 nop ba a10 code nop ra code address code nop ra code command pre arf arf mrs nop nop act mrs clk ba0=l ba1=l (h level) vdd vddq cke
data sheet. rev. 1.22, 2006-12 9 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 1. first, device core power ( v dd ) and device io power ( v ddq ) must be brought up simultaneously. typically v dd and v ddq are driven from a single power converter output. assert and hold cke and dqm to a high level. 2. after v dd and v ddq are stable and cke is high, apply stable clocks. 3. wait for 200 s while issuing nop or deselect commands. 4. issue a precharge all comm and, followed by nop or desel ect commands for at least t rp period. 5. issue two auto refresh commands, each followed by nop or deselect commands for at least t rfc period. 6. issue two mode register set comm ands for programming the mode regi ster and extended mode register, each followed by nop or deselect commands for at least t mrd period (the order in which both registers are programmed is not important). following these steps, the mobile-ram is ready for normal operation. 2.2 register definition 2.2.1 mode register the mode register is used to define the specific mode of operation of the mobile-ram . this definition includes: ? the selection of a bur st length (bits a0-a2) ? a burst type (bit a3) ? a cas latency (bits a4-a6) ? a write burst mode (bit a9) the mode register is programmed via t he mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the mode register must be loaded when all banks are idle. also , the controller must wait the specified time before initiating any subsequent operation. violatin g either of these requirements results in unspecified operation. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. table 5 mr mode register definition (ba[1:0] = 00 b ) field bits type description wb 9w write burst mode 0 burst write 1 single write cl [6:4] w cas latency 010 2 011 3 note: all other bit combinations are reserved. 03%/ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ %/ &/ %7 :%
data sheet. rev. 1.22, 2006-12 10 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.2.1.1 burst length read and write accesses to the mobile-ram are burst orient ed, with the burst length being programmable. the burst length determines the maximum number of column locations that c an be accessed for a given read or write command. burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst types. a full-page burst mode is available for the sequential burst type. when a read or write command is issued, a block of columns equal to the burst length is selected. all accesses for that burst take place within this block, meaning that the burst wrap within the block if a boundary is reached. the block is uniquel y selected by: ? a1-a9 when the burst length is set to two ? a2-a9 when the burst length is set to four ? a3-a9 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are ) used to select the starting location within the block. full page bursts wrap within the page if the boundary is reached. please note that full page burs ts do not self-terminate; this implies that full-page read or write bursts with auto prec harge are not legal commands. table 6 burst definition bt 3w burst type 0 sequential 1 interleaved bl [2:0] w burst length 000 1 001 2 010 4 011 8 111 full page (sequential burst type only) note: all other bit combinations are reserved. burst length starting column address order of accesses within a burst a2 a1 a0 sequential interleaved 2 0 0 - 1 0 - 1 1 1 - 0 1 - 0 4 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 field bits type description
data sheet. rev. 1.22, 2006-12 11 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram notes 1. for a burst length of 2, a1-ai select the two-data-element block; a0 selects the first access within the block. 2. for a burst length of 4, a2-ai select the four-data-elem ent block; a0-a1 select the first access within the block. 3. for a burst length of 8, a3-ai select the eight-data-element bloc k; a0-a2 select the first access within the block. 4. for a full page burst, a0-ai select the starting data element. 5. whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 2.2.1.2 burst type accesses within a given burst may be programme d to be either sequential or interleaved. this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by: ? the burst length ? the burst type ? the starting column address this is listed in table 6 . 2.2.1.3 read latency the read latency, or cas latency, is the delay, in clo ck cycles, between the registration of a read command and the availability of the first segment of output data . the latency can be programmed to 2 or 3 clocks. if a read command is registered at clock edge n, and the latenc y is m clocks, the data will be available with clock edge n + m (for more detailed information, please re fer to the read command description). 2.2.1.4 write burst mode when a9 = 0, the burst length programm ed via a0-a2 applies to both read and writ e bursts; when a9 = 1, write accesses consist of single data elements only. 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 full page n n n cn, cn+1, cn+2, ? not supported burst length starting column address order of accesses within a burst a2 a1 a0 sequential interleaved
data sheet. rev. 1.22, 2006-12 12 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.2.1.5 extended mode register the extended mode register contro ls additional low power features of the device. these include: ? the partial array self re fresh (pasr, bits a0-a2)) ? the temperature compensated self refresh (tcsr, bits a3-a4)) ? the drive strength selection for the dqs (bits a5-a6). the extended mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 1) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle . additionally, the controller must wait the specified time before initiating any subsequent operatio n. violating either of these requirem ents result in unspecified operation. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. table 7 emr extended mode register (ba[1:0] = 10 b ) field bits type description ds [6:5] w selectable drive strength 00 b full drive strength 01 b half drive strength note: all other bit combinations are reserved. tcsr [4:3] w temperature compensated self refresh xx superseded by on-chip te mperature sensor (see text) pasr [2:0] w partial array self refresh 000 b all banks 001 b 1/2 array (ba1 = 0) 010 b 1/4 array (ba1 = ba0 = 0) 101 b 1/8 array (ba1 = ba0 = ra12 = 0) 110 b 1/16 array (ba1 = ba0 = ra12 = ra11 = 0) note: all other bit combinations are reserved. 03%/ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ 3$65 '6 7&65
data sheet. rev. 1.22, 2006-12 13 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.2.1.6 partial array self refresh (pasr) partial array self refresh is a power-sav ing feature specific to mobile rams. wi th pasr, self refresh may be restricted to variable portions of the total array. the selection comprises: ? all four banks (default) ? two banks ? one bank ? half of one bank ? a quarter of one bank. data written to the non-activated memory sect ions will get lost after a period defined by t ref (see table 15 ). 2.2.1.7 temperature compensated self refresh (tcsr) with on- chip temperature sensor dram devices store data as electrical charge in tiny capacitors that require a period ic refresh in order to retain the stored information. this refresh requirement he avily depends on the die temperature: ? high temperatures correspond to short refresh periods ? low temperatures correspond to long refresh periods. the mobile-ram is equipped with an on-chip temperature sens or which continuously senses the actual die temperature and adjusts the refresh period in self refresh mode accordingly. this makes any programming of the tcsr bits in the extended mode register obsolete. also, it is the superior solution in terms of compatibility and power-saving, because: ? it is fully compatible to all processors t hat do not support the extended mode register ? it is fully compatible to all applications that only write a de fault (worst case) tcsr value (that is, because of the lack of an external temperature sensor) ? it does not require any processor interaction for regular tcsr updates 2.2.1.8 selectable drive strength the drive strength of the dq output buff ers is selectable via bits a5 and a6. the default value (?half drive strength?) is suitable for typical applications of a mobile-ram . for heavier loaded systems, a stronger output buffer (?full drive strength?) is available . i-v curves for full drive strength and half drive strength can be found in this document.
data sheet. rev. 1.22, 2006-12 14 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.3 state diagram figure 4 state diagram 2 % ! $ 0 o w e r / n - o d e 2 e g i s t e r 3 e t 0 o w e r a p p l i e d $ e e p 0 o w e r $ o w n $ 0 $ 3 8 - 2 3 ! # 4 3 e l f 2 e f r e s h 2 % & 3 2 % & 3 8 ) d l e $ 0 $ 3 ! u t o 2 e f r e s h 2 % & ! ! c t i v e 0 o w e r $ o w n # + % ( # + % , 2 o w ! c t i v e 7 2 ) 4 % 2 % ! $ 7 2 ) 4 % ! 2 % ! $ ! 0 r e c h a r g e 2 % ! $ 2 % ! $ ! 7 2 ) 4 % ! 2 % ! $ ! 7 2 ) 4 % ! 0 2 % 2 % ! $ ! 0 2 % ! u t o m a t i c 3 e q u e n c e # o m m a n d 3 e q u e n c e # l o c k 3 u s p e n d 2 % ! $ # l o c k 3 u s p e n d 2 % ! $ ! # l o c k 3 u s p e n d 7 2 ) 4 % # l o c k 3 u s p e n d 7 2 ) 4 % ! " 3 4 " 3 4 # + % , # + % , # + % , # + % , # + % ( # + % ( # + % ( # + % ( 0 2 % ! , , 0 r e c h a r g e ! l l " a n k s 2 % & 3 % n t e r 3 e l f 2 e f r e s h 2 % & 3 8 % x i t 3 e l f 2 e f r e s h 2 % & ! ! u t o 2 e f r e s h $ 0 $ 3 % n t e r $ e e p 0 o w e r $ o w n $ 0 $ 3 8 % x i t $ e e p 0 o w e r $ o w n # + % , % n t e r 0 o w e r $ o w n # + % ( % x i t 0 o w e r $ o w n 2 % ! $ 2 e a d w o ! u t o 0 r e c h a r g e 2 % ! $ ! 2 e a d w i t h ! u t o 0 r e c h a r g e 7 2 ) 4 % 7 r i t e w o ! u t o 0 r e c h a r g e 7 2 ) 4 % ! 7 r i t e w i t h ! u t o 0 r e c h a r g e 0 r e c h a r g e ! l l 0 2 % ! , , # + % , # + % ( 0 r e c h a r g e 0 o w e r $ o w n 7 2 ) 4 % 7 2 ) 4 % ! 7 2 ) 4 % 0 2 % 0 2 % ! # 4 ! c t i v e 0 2 % 0 r e c h a r g e " 3 4 " u r s t 4 e r m i n a t e - 2 3 - o d e 2 e g i s t e r 3 e t
data sheet. rev. 1.22, 2006-12 15 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4 commands table 8 command overview address (a0 - a12, ba0, ba1), write data (dq0 - dq15) and command inputs (cke, cs , ras , cas , we , dqm) are all registered on the positive edge of clk. figure 5 shows the basic timing parameters, which apply to all commands and operations. command cs ras cas we dqm address notes nop deselect h x x x x x 1)2) 1) cke is high for all commands shown except self refresh and deep power down. 2) deselect and nop are functionally interchangeable. no operation lhhhx x 1)2) act active (select bank and row) l l h h x bank / row 1)3) 3) ba0, ba1 provide bank address, and a0 - a12 provide row address. rd read (select bank and column and start read burst) l h l h l/h bank / col 1)4) 4) ba0, ba1 provide bank address, a0 - a9 provide column address; a10 high enables the auto precharge feature (nonpersistent), a 10 low disables the auto precharge feature. wr write (select bank and column and start write burst) l h l l l/h bank / col 1)4) bst burst terminate or deep power down l h h l x x 1)5) 5) this command is burst terminate if cke is high, deep po wer down if cke is low. the burst terminate command is defined for read or write bursts wi th auto precharge disabled only. pre precharge (deactivate row in bank or banks) l l h l x code 1)6) 6) a10 low: ba0, ba1 determine which bank is precharged.a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. arf auto refresh or self refresh (enter self refresh mode) lllhx x 1)7)8) 7) this command is auto refresh if c ke is high, self refresh if cke is low. 8) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. mrs mode register set l l l l x opcode 1)9) 9) ba0, ba1 select either the mode register (ba0 = 0, ba1 = 0) or the extended mode register (ba0 = 0, ba1 = 1); other combinati ons of ba0, ba1 are reserved; a0 - a12 provide the opcode to be written to the selected mode register. ? data write / output enable ? ? ? ? l ? 1)10) 10) dqm low: data present on dqs is written to memory during writ e cycles; dq output buffers are enabled during read cycles;dqm high: data present on dqs are masked and thus not written to memory dur ing write cycles; dq output buffers are placed in high-z state (two clocks latency) during read cycles. ? write mask / output disable (high-z) ? ? ? ? h ? 1)10)
data sheet. rev. 1.22, 2006-12 16 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 5 address / command inputs timing parameters table 9 inputs timing parameters parameter symbol - 7.5 unit notes min. max. clock cycle time cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns ? clock frequency cl = 3 f ck ? 133 mhz ? cl = 2 ? 105 mhz ? clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address and command input setup time t is 1.5 ? ns ? address and command input hold time t ih 0.8 ? ns ? $ o n g t # a r e t # , t # ( t ) 3 t ) ( t # + # , + ) n p u t
6 a l i d 6 a l i d 6 a l i d
! ! " ! " ! # 3 # + % 2 ! 3 # ! 3 7 %
data sheet. rev. 1.22, 2006-12 17 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.1 no operation (nop) the no operation (nop) command is used to perform a nop to a mobile-ram which is selected (cs = low). this prevents unwanted commands from being registered during idle states. operations alread y in progress are not affected. figure 6 no operation command 2.4.2 deselect the deselect function (cs = high) prevents new commands from being ex ecuted by the mobile-ram. the mobile-ram is effectively deselected. operations already in progress are not affected. 2.4.3 mode register set the mode register and extende d mode register are loaded via inputs a0 - a12 (see mode register descriptions in chapter 2.2 ). the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent exec utable command cannot be issued until t mrd is met. figure 7 mode register set command $ o n g t # a r e 7 % # ! 3 # 3 # + % ( i g h # , + ! ! " ! " ! 2 ! 3 $ o n g t # a r e # 3 # + % ( i g h # , + ! ! # o d e " ! " ! # o d e 7 % # ! 3 2 ! 3
data sheet. rev. 1.22, 2006-12 18 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 8 mode register definition table 10 timing parameters for m ode register set command 2.4.4 active before any read or write commands can be issued to a bank within the mobile-ram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0 - a12, ba0 and ba1 (see figure 9 ), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd figure 9 active command parameter symbol - 7.5 units notes min. max. mode register set command period t mrd 2? t ck ? # o d e - o d e 2 e g i s t e r % x t e n d e d - o d e 2 e g i s t e r s e l e c t i o n " ! " ! a n d o p c o d e ! ! t - 2 $ $ o n g t # a r e # , + # o m m a n d - 2 3 . / 0 6 a l i d ! d d r e s s # o d e 6 a l i d $ o n g t # a r e " ! " a n k ! d d r e s s 2 ! 2 o w ! d d r e s s " ! " ! " ! ! ! 2 ! 7 % # ! 3 2 ! 3 # 3 # + % ( i g h # , +
data sheet. rev. 1.22, 2006-12 19 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 10 bank activate timings table 11 timing parameters for active command parameter symbol - 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles a nd depend on the operating frequency as follows:no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active bank a to active bank b delay t rrd 15 ? ns 1) t 2 2 $ t 2 # $ $ o n g t # a r e # , + 2 $ 7 2 . / 0 . / 0 . / 0 ! # 4 . / 0 ! # 4 # o m m a n d 2 / 7 2 / 7 # / , ! ! " ! x " ! y " ! y " ! " !
data sheet. rev. 1.22, 2006-12 20 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.5 read subsequent to programming t he mode register with cas latency and burst length, read bursts are initiated with a read command, as shown in figure 11 . basic timings for the dqs are shown in figure 12 ; they apply to all read operations and therefore are omitted from all subsequent timing diagrams. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. figure 11 read command figure 12 basic read timing pa rameters for dqs " ! " ! " ! 7 % # + % ( i g h # , + 2 ! 3 # ! 3 ! ! # ! $ o n g t # a r e " ! " a n k ! d d r e s s # ! # o l u m n ! d d r e s s ! 0 ! u t o 0 r e c h a r g e ! ! 0 $ i s a b l e ! 0 % n a b l e ! 0 # 3 t , : t ! # t ! # t (: # , + $ o n g t # a r e t $ 1 : t / ( t / ( $ 1 - $ 1 $ / n $ / n
data sheet. rev. 1.22, 2006-12 21 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 12 timing parameters for read during read bursts, the valid data-out el ement from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive clock edge. upon completion of a read burst, assuming no other read command has been initiated, the dqs go to high-z state. figure 13 and figure 14 show single read bursts for each supported cas latency setting. figure 13 single read burst (cas latency = 2) parameter symbol - 7.5 units notes min. max. access time from clk cl = 3 t ac ? 5.4 ns ? cl = 2 t ac ? 6.0 ns dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns ? data out hold time t oh 2.5 ? ns ? dqm to dq high-z delay (read commands) t dqz ?2 t ck ? active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles a nd depend on the operating frequency as follows:no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) precharge command period t rp 19 ? ns 1) " a ! # o l n b a n k ! c o l u m n n $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n $ o n g t # a r e # , t 2 # $ t 2 ! 3 t 2 # t 20 # , + # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 ! d d r e s s " a ! 2 o w b " a ! # o l n " a ! 2 o w x ! ! 0 0 r e " a n k ! 0 r e ! l l $ i s ! 0 2 o w x 2 o w b ! 0 $ / n $ / n $ / n $ / n $ 1 ! 0 ! u t o 0 r e c h a r g e $ i s ! 0 $ i s a b l e ! u t o 0 r e c h a r g e
data sheet. rev. 1.22, 2006-12 22 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 14 single read burst (cas latency = 3) data from any read burst may be concatenated with data fr om a subsequent read command. in either case, a continuous flow of data can be maintained. a read command can be in itiated on any clock cycle follo wing a previous read command and may be performed to the same or a different (active) bank. t he first data element from the new burst follows either the las t element of a completed burst ( figure 15 ) or the last desired data element of a longer burst which is being truncated ( figure 16 ). the new read command should be issued x cycles af ter the first read command (where x equals the number of desired data elements). figure 15 consecutive read bursts " a ! # o l n b a n k ! c o l u m n n $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n $ o n g t # a r e # , t 2 # $ t 2 0 t 2 ! 3 t 2# # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 . / 0 . / 0 # , + ! 0 ! u t o 0 r e c h a r g e $ i s ! 0 $ i s a b l e ! u t o 0 r e c h a r g e ! d d r e s s ! ! 0 0 r e " a n k ! 0 r e ! l l $ i s ! 0 $ 1 $ / n $ / n $ / n $ / n " a ! 2 o w b 2 o w b " a ! 2 o w x 2 o w x " a ! # o l n ! 0 " a ! # o l n b " a n k ! # o l u m n n b $ / n b $ a t a / u t f r o m c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n b $ o n g t # a r e # , + # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 2 % ! $ . / 0 ! d d r e s s " a ! # o l b " a ! # o l n $ 1 $ / n $ / n $ / n $ / n $ / b $ / b $ / b $ 1 $ / n $ / n $ / n $ / n $ / b $ / b
data sheet. rev. 1.22, 2006-12 23 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 16 random read bursts non-consecutive read bursts are shown in figure 17 . figure 17 non-consecutive read bursts " a ! # o l n e t c " a n k ! # o l u m n n e t c $ / n e t c $ a t a / u t f r o m c o l u m n n e t c " u r s t , e n g t h i n t h e c a s e s h o w n b u r s t s a r e t e r m i n a t e d b y c o n s e c u t i v e 2 % ! $ c o m m a n d s s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / m $ o n g t # a r e # , + # , # , # o m m a n d 2 % ! $ . / 0 . / 0 . / 0 . / 0 2 % ! $ 2 % ! $ 2 % ! $ . / 0 " a ! # o l n " a ! # o l a " a ! # o l x " a ! # o l m ! d d r e s s $ 1 $ / m $ / m $ / a $ / n $ / x $ / m $ / m $ 1 $ / m $ / a $ / n $ / x $ / m $ / m " a ! # o l n b " a n k ! # o l u m n n b $ / n b $ a t a / u t f r o m c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n b # , # , $ o n g t # a r e # , + # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 2 % ! $ . / 0 " a ! # o l n ! d d r e s s " a ! # o l b $ 1 $ / n $ / n $ / n $ / n $ / b $ / b $ 1 $ / n $ / n $ / n $ / n $ / b
data sheet. rev. 1.22, 2006-12 24 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.5.1 read burst termination data from any read burst may be truncated using the burst terminate command (see page 35 ), provided that auto precharge was not activated. the burst terminate latency is equal to the cas latency (that is, the burst terminate command must be issued x clock cycles before the clock edge at which the last desired data elem ent is valid, where x equals the cas latency for read bursts minus 1). this is shown in figure 18 . the burst terminate command may be used to terminate a full-page read which does not self-terminate. figure 18 terminating a read burst 2.4.5.2 clock suspend mode for read cycles clock suspend mode allows the extension of any read burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse(s) will be ignored and data on dq will remain driven, as shown in figure 19 . " a ! # o l n " a n k ! # o l u m n n $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n 4 h e b u r s t i s t e r m i n a t e d a f t e r t h e r d d a t a e l e m e n t $ o n g t # a r e # , + # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 " 3 4 . / 0 ! d d r e s s " a ! # o l n $ 1 $ / n $ / n $ / n $ 1 $ / n $ / n $ / n
data sheet. rev. 1.22, 2006-12 25 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 19 clock suspend mode for read bursts 2.4.5.3 read - dqm operation dqm may be used to suppress read data and place the output bu ffers into high-z state. the generic timing parameters as listed in table 12 also apply to this dqm operation. the read burst in pr ogress is not affected and will continue as programmed. figure 20 read burst - dqm operation " a ! # o l n e t c " a n k ! # o l u m n n e t c $ / n e t c $ a t a / u t f r o m c o l u m n n e t c # , i n t h e c a s e s h o w n # l o c k s u s p e n d l a t e n c y t # 3 , i s c l o c k c y c l e $ o n g t # a r e # , + t # 3 , t # 3 , t # 3 , # + % i n t e r n a l c l o c k # o m m a n d 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 " a ! # o l n ! d d r e s s $ 1 $ / n $ / n $ / n $ / n " a ! # o l n b a n k ! c o l u m n n $ / n $ a t a / u t f r o m c o l u m n n # , i n t h e c a s e s h o w n $ 1 - r e a d l a t e n c y t $ 1 : i s c l o c k c y c l e s $ o n g t # a r e # , + # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ 1 - t $ 1 : ! d d r e s s " a ! # o l n $ 1 $ / n $ / n $ / n
data sheet. rev. 1.22, 2006-12 26 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.5.4 read to write a read burst may be followed by or truncated with a wr ite command. the write command can be performed to the same or a different (active) bank. care must be taken to avoid bus contention on the dqs; therefore it is recommended that the dqs are held in high-z state for a minimum of 1 clock cycle. this can be achieved by either delaying the write command, or suppressing the data-out from the read by pulling dqm high two clock cycles prior to the write command, as shown in figure 21 . with the registration of the write command, dqm acts as a write mask: when asserted high, input data will be masked and no write will be performed. figure 21 read to write timing " a ! # o l n b b a n k ! c o l u m n n b $ / n $ a t a / u t f r o m c o l u m n n $ ) b $ a t a ) n t o c o l u m n b $ 1 - i s a s s e r t e d ( ) ' ( t o s e t $ 1 s t o ( i g h : s t a t e f o r c l o c k c y c l e p r i o r t o t h e 7 2 ) 4 % c o m m a n d $ o n g t # a r e # , + # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % ! d d r e s s " a ! # o l b " a ! # o l n $ 1 - $ 1 $ / n $ ) b $ ) b $ / n ( i g h : $ ) b $ 1 $ ) b $ ) b $ / n ( i g h : $ ) b
data sheet. rev. 1.22, 2006-12 27 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.5.5 read to precharge a read burst may be followed by, or truncated with a precharge command to the same bank, provided that auto precharge was not activated. this is shown in figure 22 . the precharge command should be issued x clock cycles before the clock edge at which the la st desired data element is valid (where x equals the cas latency for read bursts minus 1). following the precharge command, a subsequent active command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it require s that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 22 read to precharge timing " a ! # o l n b a n k ! c o l u m n n " ! ! m 2 o w b a n k ! r o w x $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n # ! 3 l a t e n c y i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n $ o n g t # a r e # , # , + t 2 0 # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 ! # 4 0 2 % " a ! 2 o w a ! d d r e s s " a ! " a ! # o l n $ i s ! 0 0 r e " a n k ! 0 r e ! l l ! ! 0 ! 0 $ 1 $ / n $ / n $ / n $ / n
data sheet. rev. 1.22, 2006-12 28 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.6 write write bursts are initiated with a write command, as shown in figure 23 . basic timings for the dqs are shown in figure 24 ; they apply to all write operations. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the write burst. for the generic write commands used in the following illustrations, auto precharge is disabled. figure 23 write command figure 24 basic write timing pa rameters for dqs during write bursts, the first valid data- in element is registered coincident with the write command, and subsequent data elements are registered on each successive positive edge of clk. upon completion of a burst, assuming no other commands have been initiated, the dqs remain in high-z state, and any additional input data is ignored. figure 25 and figure 26 show a single write burst for each supported cas latency setting. " ! " ! " ! # 3 # + % ( i g h # , + 2 ! 3 # ! 3 ! ! # ! $ o n g t # a r e " ! " a n k ! d d r e s s # ! # o l u m n ! d d r e s s ! 0 ! u t o 0 r e c h a r g e ! ! 0 $ i s a b l e ! 0 % n a b l e ! 0 7 % # , + $ o n g t # a r e t ) 3 t ) ( t ) 3 t ) ( $ 1 - $ 1 $ ) n $ ) n
data sheet. rev. 1.22, 2006-12 29 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 13 timing parameters for write figure 25 write burst (cas latency = 2) parameter symbol - 7.5 units notes min. max. dq and dqm input setup time t is 1.5 ? ns ? dq and dqm input hold time t ih 0.8 ? ns ? dqm write mask latency t dqw 0? t ck ? active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles a nd depend on the operating frequency as follows:no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1) " a ! # o l n b a n k ! c o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ o n g t # a r e # , + t 2 # $ t 2 ! 3 t 2 # t 20 t 7 2 # o m m a n d . / 0 7 2 ) 4 % . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 . / 0 ! d d r e s s " a ! 2 o w x " a ! # o l n " a ! 2 o w b 2 o w x 2 o w b $ i s ! 0 ! 0 0 r e " a n k ! 0 r e ! l l ! ! 0 $ 1 $ ) n $ ) n $ ) n $ ) n
data sheet. rev. 1.22, 2006-12 30 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 26 write burst (cas latency = 3) data for any write burst may be concatenated with or trunc ated with a subsequent write command. in either case, a continuous flow of input data can be maintained. a write command can be issued on any positive edge of clock following the previous write command. the first data element from the new bur st is applied after either the last element of a completed burst ( figure 27 ) or the last desired data element of a longer burst which is being truncated ( figure 28 ). the new write command should be issued x cycles after the first write comm and (where x equals the number of desired data elements). figure 27 consecutive write bursts " a ! # o l n b a n k ! c o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ o n g t # a r e t 2 # $ t 2 ! 3 t 2 # t 2 0 t 7 2 # , + # o m m a n d . / 0 7 2 ) 4 % . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 . / 0 . / 0 . / 0 ! d d r e s s " a ! 2 o w n " a ! # o l n " a ! 2 o w b 0 r e " a n k ! 0 r e ! l l 2 o w x $ i s ! 0 ! 0 2 o w b ! ! 0 $ 1 $ ) n $ ) n $ ) n $ ) n " a ! # o l n b " a n k ! # o l u m n n b $ ) n b $ a t a ) n t o c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n b # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % 7 2 ) 4 % # , + ! d d r e s s " a ! # o l b " a ! # o l n $ 1 $ ) n $ ) n $ ) n $ ) n $ ) b $ ) b $ ) b $ ) b $ o n g t # a r e
data sheet. rev. 1.22, 2006-12 31 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 28 random write bursts non-consecutive write bursts are shown in figure 29 . figure 29 non-consecutive write bursts " a ! # o l n e t c " a n k ! # o l u m n n e t c $ ) n e t c $ a t a ) n t o c o l u m n n e t c " u r s t , e n g t h i n t h e c a s e s h o w n b u r s t s a r e t e r m i n a t e d b y c o n s e c u t i v e 7 2 ) 4 % c o m m a n d s s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) m $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % 7 2 ) 4 % 7 2 ) 4 % 7 2 ) 4 % ! d d r e s s " a ! # o l m " a ! # o l x " a ! # o l a " a ! # o l n $ 1 $ ) n $ ) a $ ) x $ ) m $ ) m $ ) m $ ) m " a ! # o l n b " a n k ! # o l u m n n b $ ) n b $ a t a ) n t o c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n b $ o n g t # a r e # , + 7 2 ) 4 % # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % " a ! # o l n ! d d r e s s " a ! # o l b $ ) b $ 1 $ ) n $ ) n $ ) n $ ) n $ ) b $ ) b
data sheet. rev. 1.22, 2006-12 32 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.6.1 write burst termination data from any write burst may be truncated using the burst terminate command (see page 35 ), provided that auto precharge was not activated. the input data provided coincid ent with the burst terminate command will be ignored. this is shown in figure 30 . the burst terminate command may be used to te rminate a full-page write which does not self- terminate. figure 30 terminating a write burst 2.4.6.2 clock suspend mode for write cycles clock suspend mode allows the extension of any write burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse( s) will be ignored and no data will be captured, as shown in figure 31 . " a ! # o l n " a n k ! # o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e w r i t t e n i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n 4 h e b u r s t i s t e r m i n a t e d a f t e r t h e r d d a t a e l e m e n t $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 " 3 4 . / 0 . / 0 7 2 ) 4 % . / 0 ! d d r e s s " a ! # o l n $ 1 $ ) n $ ) n $ ) n
data sheet. rev. 1.22, 2006-12 33 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 31 clock suspend mode for write bursts 2.4.6.3 write - dqm operation dqm may be used to mask write data: when asserted high, inpu t data will be masked and no write will be performed. the generic timing parameters as listed in table 13 also apply to this dqm operation. th e write burst in progr ess is not affected and will continue as programmed. figure 32 write burst - dqm operation " a ! # o l n e t c " a n k ! # o l u m n n e t c $ / n e t c $ a t a / u t f r o m c o l u m n n e t c # , i n t h e c a s e s h o w n # l o c k s u s p e n d l a t e n c y t # 3 , i s c l o c k c y c l e # , + # + % i n t e r n a l c l o c k # o m m a n d . / 0 . / 0 . / 0 7 2 ) 4 % . / 0 " a ! # o l n ! d d r e s s $ 1 $ ) n $ ) n $ ) n $ o n g t # a r e t # 3 , t # 3 , t # 3 , " a ! # o l n " a n k ! # o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n w i t h t h e f i r s t e l e m e n t $ ) n b e i n g m a s k e d $ 1 - w r i t e l a t e n c y i s c l o c k c y c l e s $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % ! d d r e s s " a ! # o l n $ 1 - $ 1 $ ) n $ ) n $ ) n
data sheet. rev. 1.22, 2006-12 34 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.6.4 write to read a write burst may be followed by, or truncated with a r ead command. the read command can be performed to the same or a different (active) bank. with the registration of the read command, data inputs will be ignored and no write will be performed, as shown in figure 33 . figure 33 write to read timing 2.4.6.5 write to precharge a write burst may be followed by, or truncated with a precharge command to the same bank, provided that auto precharge was not activated. this is shown in figure 34 . the precharge command should be issued t wr after the clock edge at where the la st desired data element of the write burst was registered. additionally, when truncating a write bu rst, dqm must be pulled to mask input data presented during t wr prior to the precharge command. following the pre- charge command, a subsequent active command to the same bank cannot be issued until t rp is met. in the case of a write being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same write bur st with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses to be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. " a ! # o l n b b a n k ! c o l u m n n b $ ) n $ a t a ) n t o c o l u m n n $ / b $ a t a / u t f r o m c o l u m n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ / b $ ) n i s i g n o r e d d u e t o 2 % ! $ c o m m a n d . o $ 1 - m a s k i n g r e q u i r e d a t t h i s p o i n t $ o n g t # a r e # , + 7 r i t e d a t a a r e i g n o r e d # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % ! d d r e s s " a ! # o l b " a ! # o l n $ 1 $ / b $ / b $ / b $ ) n $ ) n $ ) n ( i g h : $ 1 $ / b $ ) b $ ) n $ ) n $ ) n ( i g h :
data sheet. rev. 1.22, 2006-12 35 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 34 write to precharge timing 2.4.7 burst terminate the burst terminate command is used to truncate read or write bursts (with auto precharge disabled). the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in figure 18 and figure 30 , respectively. the burst terminate command is not allowed for truncation of read or write bursts with auto precharge enabled. figure 35 burst terminate command " a ! # o l n b a n k ! c o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ ) n i s m a s k e d d u e t o $ 1 - p u l l e d ( ) ' ( d u r i n g t 7 2 p e r i o d p r i o r t o 0 2 % # ( ! 2 ' % c o m m a n d $ o n g t # a r e $ 1 $ ) n $ ) n $ ) n t 2 0 t 7 2 # , + $ 1 - # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 ! # 4 0 2 % 7 2 ) 4 % ! d d r e s s " a ! # o l n " a ! 2 o w a " a ! $ i s ! 0 0 r e " a n k ! 0 r e ! l l ! ! 0 ! 0 ! 0 ! u t o 0 r e c h a r g e $ i s ! 0 $ i s a b l e ! u t o 0 r e c h a r g e $ o n g t # a r e # ! 3 # 3 # + % ( i g h # , + ! ! " ! " ! 7 % 2 ! 3
data sheet. rev. 1.22, 2006-12 36 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.8 precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no o pen row in that bank, or if the previously open row is already in the process of precharging. figure 36 precharge command 2.4.8.1 auto precharge auto precharge is a feature which performs the same individual-bank prec harge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or wr ite burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensu res that the precharge is init iated at the earliest valid stage within a burst. the user must not issue another co mmand to the same bank until the precharge ( t rp ) is completed. auto precharge is equivalent to an explicit precharge command being issued at the ear liest possible time, as described for each burst type. " ! " ! " ! # 3 # + % ( i g h # , + $ o n g t # a r e " ! " a n k ! d d r e s s i f ! , o t h e r w i s e $ o n g t # a r e 2 ! 3 # ! 3 7 % ! / n e " a n k ! l l " a n k s ! ! ! !
data sheet. rev. 1.22, 2006-12 37 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 14 timing parameters for precharge 2.4.8.2 concurrent auto precharge a read or write burst with auto precharge enabled can be interrupted by a subsequent read or write command issued to a different bank. figure 37 shows a read with auto precharge to bank n, interr upted by a read (with or without auto precharge) to bank m. the read to bank m will interrupt the read to bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. figure 38 shows a read with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin when the write to bank m is registered. dq m should be pulled high two clock cycles prior to the write to prevent bus contention. figure 39 shows a write with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the precharge to bank n will begin t wr after the new command to bank m is register ed. the last valid data-in to bank n is one clock cycle prior to the read to bank m. figure 40 shows a write with auto precharge to bank n, interrupt ed by a write (with or without auto precharge) to bank m. the precharge to bank n will begin t wr after the write to bank m is registered. the last valid data-in to bank n is one clock cycle prior to the write to bank m. figure 37 read with auto prechar ge interrupted by read parameter symbol - 7.5 units notes min. max. active to precharge command period t ras 45 100k ns 1) 1) these parameters account for the number of clock cycles a nd depend on the operating frequency as follows:no. of clock cycles = specified delay / clock period; round up to next integer. write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1) 2 $ ! 0 2 e a d w i t h ! u t o 0 r e c h a r g e 2 % ! $ 2 e a d w i t h o r w i t h o u t ! u t o 0 r e c h a r g e # , a n d " u r s t , e n g t h i n t h e c a s e s h o w n 2 e a d w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 2 e a d t o b a n k m $ o n g t # a r e # , # , + # o m m a n d 2 $ ! 0 . / 0 . / 0 . / 0 2 % ! $ . / 0 . / 0 . / 0 ! d d r e s s " a n k n # o l b " a n k m # o l x $ 1 $ / b $ / b $ / x $ / x $ / x t 20 b a n k n
data sheet. rev. 1.22, 2006-12 38 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 38 read with auto precharge interrupted by write figure 39 write with auto precharge interrupted by read 2 $ ! 0 2 e a d w i t h ! u t o 0 r e c h a r g e 7 2 ) 4 % 7 r i t e w i t h o r w i t h o u t ! u t o 0 r e c h a r g e # , a n d " u r s t , e n g t h i n t h e c a s e s h o w n 2 e a d w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 7 r i t e t o b a n k m $ o n g t # a r e # , $ 1 - # , + # o m m a n d . / 0 2 $ ! 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % . / 0 ! d d r e s s " a n k m # o l x " a n k n # o l b $ 1 $ / b $ ) x $ ) x $ ) x $ ) x t 20 b a n k n 7 2 ! 0 7 r i t e w i t h ! u t o 0 r e c h a r g e 2 % ! $ 2 e a d w i t h o r w i t h o u t ! u t o 0 r e c h a r g e # , a n d " u r s t , e n g t h i n t h e c a s e s h o w n 7 r i t e w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 2 e a d t o b a n k m $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 . / 0 2 % ! $ . / 0 ! d d r e s s " a n k n # o l b " a n k m # o l x . / 0 . / 0 7 2 ! 0 t 7 2 b a n k n t 20 b a n k n $ 1 $ / x $ / x $ / x $ / b $ / b $ / x # ,
data sheet. rev. 1.22, 2006-12 39 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 40 write with auto precharge interrupted by write 2.4.9 auto refresh and self refresh the mobile-ram requires a refresh of all rows in a rollin g interval. each refresh is generated in one of two ways: ? by an explicit auto refresh command ? by an internally timed event in self refresh mode. 2.4.9.1 auto refresh auto refresh is used during normal operation of the mobile-ram. the command is nonpersistent, so it must be issued each time a refresh is required. a minimum row cycle time ( t rc ) is required between two auto refresh commands. the same rule applies to any access command after the auto refresh operation. all banks must be precharged prior to the auto refresh command. the refresh addressing is gener ated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. th e mobile-ram requires auto refresh cycles at an aver age periodic interval of 7.8 s (max.). partial array mode has no influence on auto refresh mode. figure 41 auto refresh command 7 2 ! 0 7 r i t e w i t h ! u t o 0 r e c h a r g e 7 2 ) 4 % 7 r i t e w i t h o r w i t h o u t ! u t o 0 r e c h a r g e " u r s t , e n g t h i n t h e c a s e s h o w n 7 r i t e w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 7 r i t e t o b a n k m $ o n g t # a r e # , + t 20 b a n k n t 7 2 b a n k n # o m m a n d . / 0 . / 0 . / 0 7 2 ) 4 % . / 0 7 2 ! 0 . / 0 . / 0 ! d d r e s s " a n k n # o l b " a n k m # o l x $ 1 $ ) b $ ) b $ ) x $ ) x $ ) x $ ) x $ o n g t # a r e # 3 # + % ( i g h # , + ! ! " ! " ! # ! 3 7 % 2 ! 3
data sheet. rev. 1.22, 2006-12 40 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 42 auto refresh 2.4.9.2 self refresh the self refresh command can be used to retain data in the mobile-ram, even if the rest of the system is powered down. when in the self refresh mode, the mobile-ram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is low. input si gnals except cke, are ?don?t care? during self refresh. the procedure for exiting self refresh requires a stable clock prior to cke returning high. once cke is high, nop commands must be issued for t rc because time is required for a completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally-timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, an extra auto refresh command is recommended. figure 43 self refresh entry command " a ! 2 o w n b a n k ! r o w n t 2 0 t 2 # t 2 # $ o n g t # a r e $ 1 ( i g h : ! ! 0 2 o w n 0 r e ! l l ! d d r e s s " a ! 2 o w n # o m m a n d . / 0 ! 2 & . / 0 . / 0 . / 0 . / 0 0 2 % ! 2 & ! # 4 # , + $ o n g t # a r e # 3 # + % # , + ! ! " ! " ! # ! 3 7 % 2 ! 3
data sheet. rev. 1.22, 2006-12 41 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 44 self refresh entry and exit table 15 timing parameters for auto refresh and self refresh parameter symbol - 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows:no. of clock cycles = specified delay / clock period; round up to next integer. precharge command period t rp 19 ? ns 1) refresh period (8192 rows) t ref ?64ms 1) self refresh exit time t srex 1? t ck 1) t 2 0 t 2 # t 2 # 3 e l f 2 e f r e s h % n t r y # o m m a n d 3 e l f 2 e f r e s h % x i t # o m m a n d % x i t f r o m 3 e l f 2 e f r e s h ! n y # o m m a n d ! u t o 2 e f r e s h 2 e c o m m e n d e d $ o n g t # a r e t 3 2 % 8 ! ! 0 0 r e ! l l 2 o w n # , + # + % # o m m a n d . / 0 ! 2 & . / 0 . / 0 . / 0 0 2 % ! 2 & ! # 4 . / 0 ! d d r e s s " a ! 2 o w n $ 1 ( i g h :
data sheet. rev. 1.22, 2006-12 42 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.10 power down power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power- down. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk and cke. cke low mu st be maintained during power-down. power-down duration is limited by the refresh requirements of the device ( t ref ). the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). one clock delay is required for power down entry and exit. figure 45 power down entry command figure 46 power down entry and exit $ o n g t # a r e # 3 # + % # , + 2 ! 3 ! ! " ! " ! 7 % # ! 3 0 r e c h a r g e 0 o w e r $ o w n m o d e s h o w n a l l b a n k s a r e i d l e a n d t 2 0 m e t $ongt#are ! n y when0ower$own%ntry#ommandisissued #ommand % n t r y 0ower$own t % x i t f r o m 20 ( i g h : 0ower$own ! ! 0 6 a l i d $1 ! d d r e s s 6 a l i d 0re!ll #ommand ./0 ./0 6 a l i d ./0 02% #+% #,+
data sheet. rev. 1.22, 2006-12 43 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 2.4.10.1 deep power down the deep power down mode is an unique function on low po wer sdram devices with extremely low current consumption. deep power down mode is entered using the burst terminate command (see figure 35 ) except that cke is low. all internal voltage generators inside the device are stopped and a ll memory data is lost in this mode. to enter the deep power down mode all banks must be precharged. the deep power down mode is asynchronously exited by assert ing cke high. after the exit, the same command sequence as that used power-up initialization, including the 200s initial pause, must be applied before any other command may be issued (see figure 3 and figure 4 ). 2.5 function truth tables table 16 current state bank n - command to bank n current state cs ras cas we command / action notes any h x x x deselect (nop / continue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table is bank-specific, except wher e noted (that is, the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3) current state definitions see table 17 4) the following states must not be interrupted by a command iss ued to the same bank. deselect or nop commands, or allowable commands to the other bank should be issu ed on any clock edge occurring during these st ates. allowable commands to the other ba nk are determined by its current state and according to table 20 , see also table 18 5) the following states must not be interrupted by any exec utable command; deselect or nop commands must be applied on each positive clock edge duri ng these states, see table 19 6) all states and sequences not shown are illegal or reserved. l h h h no operation (nop / continue previous operation) 1)2) to 6) idle l l h h active (select and activate row) 1)2) to 6) l l l h auto refresh 1)2) to 6) , 7) 7) not bank-specific; requires that all banks are idle and no bursts are in progress. l l l l mode register set 1)2) to 6) 7) l l h l precharge 1) to 6) , 8) 8) same as nop command in that state. row active l h l h read (select column and start read burst) 1) to 6) , 9) l h l l write (select column and start write burst) 1) to 6) , 9) l l h l precharge (deactivate row in bank or banks) 1) to 6) , 10) read (auto- precharge disabled) l h l h read (select column and start new read burst) 1) to 6) , 9) l h l l write (select column and start new write burst) 1) to 6) , 9) l l h l precharge (truncate read burst, start precharge) 1) to 6) , 10) l h h l burst terminate 1) to 6) , 11) write (auto- precharge disabled) l h l h read (select column and start read burst) 1) to 6) , 9) l h l l write (select column and start write burst) 1) to 6) , 9) l l h l precharge (truncate writ e burst, start precharge) 1) to 6) , 10) l h h l burst terminate 1) to 6) , 11)
data sheet. rev. 1.22, 2006-12 44 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 17 current state definitions table 18 state definitions 2 table 19 state defintions 3 9) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10) may or may not be bank-specific. if mu ltiple banks are to be precharged, each must be in a valid state for precharging. 11) not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. idle the bank has been precharged, and t rp has been met. row active a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read a read burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. write a write burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. precharging starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the ?idle? state. row activating starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read with ap enabled starts with registration of a read comma nd with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. refreshing starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram is in the ?all banks idle? state. accessing mode register starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the sdram is in the ?all banks idle? state. precharging all starts with registration of a pr echarge all command and ends when t rp is met. once t rp is met, all banks are in the idle state.
data sheet. rev. 1.22, 2006-12 45 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 20 current state bank n - command to bank m (different bank) current state cs ras cas we command / action notes any h x x x deselect (nop / continue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table describes alternate bank op eration, except where noted (that is, the current state is for bank n and the commands shown are those allowed to be issued to bank m (assumi ng that bank m is in such a state that the given command is allowable)). exceptions are covered in the notes below. 3) current state definitions see table 21 4) auto refresh, self refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved. l h h h no operation (nop / continue previous operation) 1) to 6) idle x x x x any command otherwise allowed to bank n 1) to 6) row activating, active, or precharging l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) 7) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 8) 8) requires appropriate dqm masking. l l h l precharge (deactivate row in bank or banks) 1) to 6) write (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read(with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) , 9) 9) concurrent auto precharge: bank n will start precharging when its burst has been interrupted by a read or write command to ba nk m. l h l l write (select column and start write burst) 1) to 9) l l h l precharge (deactivate row in bank or banks) 1) to 6) write(with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) , 9) l h l l write (select column and start write burst) 1) to 7) , 9) l l h l precharge (deactivate row in bank or banks) 1) to 6)
data sheet. rev. 1.22, 2006-12 46 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 21 current state definitions table 22 truth table - cke idle the bank has been precharged, and t rp has been met row active a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress read a read burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated write a write burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated read with ap enabled starts with registration of a read comma nd with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state write with ap enabled starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state cken-1 cken current state command action notes l l power down x maintain power down 1)2)3)4) 1) cken is the logic state of cke at clock edge n; c ken-1 was the state of cke at the previous clock edge. 2) current state is the state immediately prior to clock edge n. 3) command n is the command registered at clock edge n; action n is a result of command n. 4) all states and sequences not shown are illegal or reserved. self refresh x maintain self refresh 1) to 4) clock suspend x maintain clock suspend 1) to 4) deep power down x maintain deep power down 1) to 4) l h power down deselect or nop exit power down 1) to 4) self refresh deselect or nop exit self refresh 1) to 5) 5) deselect or nop commands should be iss ued on any clock edges occurring during t rc period. clock suspend x exit clock suspend 1) to 4) deep power down x exit deep power down 1) to 4) , 6) 6) exit from deep power down requires the same command sequence as for power-up initialization. h l all banks idle deselect or no p enter precharge power down 1) to 4) bank(s) active deselect or nop enter active power down 1) to 4) all banks idle auto refresh enter self refresh 1) to 4) read / write burst (valid) enter clock suspend 1) to 4) h hsee table 16 and table 20 1) to 4)
data sheet. rev. 1.22, 2006-12 47 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 3 electrical characteristics 3.1 operating conditions table 23 absolute maximum ratings attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods m ay affect device reliability.maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 24 pin capacitances parameter symbol values unit min. max. power supply voltage v dd -0.3 2.7 v power supply voltage for output buffer v ddq -0.3 2.7 v input voltage v in -0.3 v ddq + 0.3 v output voltage v out -0.3 v ddq + 0.3 v operation case temperature commercial t c 0+70c extended t c -25 +85 c storage temperature t stg -55 +150 c power dissipation p d ?0.7w short circuit output current i out ?50ma parameter symbol values unit notes 1)2) 1) these values are not subject to production te st but verified by device characterization. 2) input capacitance is measur ed according to jep147 with v dd , v ddq applied and all other pins (except the pin under test) floating. dq?s should be in high impedance state. this may be achieved by pulling cke to low level. min. max. input capacitance: clk c i1 3.0 6.0 pf ? input capacitance: all other input c i2 3.0 6.0 pf input/output capacitance: dq c io 3.0 5.0 pf input/output capacitance: ldqm and udqm c io2 1.5 3.0 pf
data sheet. rev. 1.22, 2006-12 48 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 25 electrical characteristics 3.2 ac characteristics table 26 ac characteristics parameter symbol values unit notes 1) 1) 0 ? c t c 70 c (comm.); -25 c t c 85 c (ext.); all voltages referenced to v ss . v ss and v ssq must be at same potential. min. max. power supply voltage v dd 1.7 1.95 v ? power supply voltage for dq output buffer v ddq 1.7 1.95 v ? input high voltage v ih 0.8 v ddq v ddq + 0.3 v 2) 2) v ih may overshoot to v dd + 0.8 v for pulse width < 4 ns; v il may undershoot to -0.8 v for pulse width < 4 ns.pulse width measured at 50% with amplitude measured between peak voltage and dc reference level. input low voltage v il -0.3 0.3 v ? output high voltage v oh v ddq - 0.2 ? v ? output low voltage v ol ?0.2v? input leakage current i il -1.0 1.0 ? ? output leakage current i ol -1.5 1.5 a? parameter symbol - 7.5 unit notes 1)2)3)4) min. max. clock cycle time cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns clock frequency cl = 3 f ck ?133mhz? cl = 2 ? 105 mhz access time from clk cl = 3 cl = 2 t ac ?6.0ns 5) ?7.0ns clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address, data and command input setup time t is 1.5 ? ns 6) address, data and command input hold time t ih 0.8 ? ns 6) mode register set command period t mrd 2? t ck ? dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns ? data out hold time t oh 2.5 ? ns 5)6) dqm to dq high-z delay (read commands) t dqz ?2 t ck ? dqm write mask latency t dqw 0? t ck ?
data sheet. rev. 1.22, 2006-12 49 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 47 3.3 operating currents table 27 maximum operating currents active to active command period t rc 67 ? ns 7) active to read or write delay t rcd 19 ? ns 7) active bank a to active bank b delay t rrd 15 ? ns 7) active to precharge command period t ras 45 100k ns 7) write recovery time t wr 14 ? ns 8) precharge command period t rp 19 ? ns 7) refresh period (8192 rows) t ref ?64 ms? self refresh exit time t srex 1? t ck ? 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = v ddq = 1.70 v to 1.95 v; 2) all parameters assumes pr oper device initialization. 3) ac timing tests measured at 0.9 v. 4) the transition time is measured between v ih and v il ; all ac characteristics assume t t = 1 ns. 5) specified t ac and t oh parameters are measured with a 30 pf capacitive load only as shown in figure 47 . 6) if t t > 1 ns, a value of [0.5 x( t t - 1)] ns has to be added to this parameter. 7) these parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round up to next integer. 8) the write recovery time of t wr = 14 ns allows the use of one clock cycle for the write recovery time when f ck 72 mhz. with f ck > 72 mhz two clock cycles for t wr are mandatory. qimonda technologies recommends to use tw o clock cycles for the write recovery time in all applications. parameter & test conditio ns symbol valuea unit notes 1) - 7.5 operating current: one bank: active / read / precharge, bl = 1, t rc = t rcmin i dd1 120 ma 2)3) precharge power-down standby current: all banks idle, cs v ihmin , cke v ilmax , inputs changing once every two clock cycles i dd2p 1.2 ma ? precharge power-down standby current with clock stop: all banks idle, cs v ihmin , cke v ilmax , all inputs stable i dd2ps 1.0 ma ? parameter symbol - 7.5 unit notes 1)2)3)4) min. max. 30 pf i/o
data sheet. rev. 1.22, 2006-12 50 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram table 28 self refresh currents precharge non power-down standby current: all banks idle, cs v ihmin , cke v ihmin , inputs changing once every two clock cycles i dd2n 26 ma ? precharge non power-down standby current with clock stop: all banks idle, cs v ihmin , cke v ihmin , all inputs stable i dd2ns 2.0 ma ? active power-down standby current: one bank active, cs v ihmin , cke v ilmax , inputs changing once every two clock cycles i dd3p 2.0 ma ? active power-down standby current with clock stop: one bank active, cs v ihmin , cke v ilmax , all inputs stable i dd3ps 1.5 ma ? active non power-down standby current: one bank active, cs v ihmin , cke v ihmin , inputs changing once every two clock cycles i dd3n 30 ma ? active non power-down standby current with clock stop: one bank active, cs v ihmin , cke v ihmin , all inputs stable i dd3ns 3.0 ma ? operating burst read current: all banks active; continuous burst read, inputs changing once every two clock cycles i dd4 90 ma ? auto-refresh current: t rc = t rcmin , ?burst refresh?, inputs changing once every two clock cycles i dd5 180 ma ? self refresh current:self refresh mode, cs v ihmin , cke v ilmax , all inputs stable i dd6 see table 28 ? deep power down current i dd7 25 a 4) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = v ddq = 1.70 v to 1.95 v;recommended operating conditions unless otherwise noted 2) these values are measured with t ck = 7.5 ns 3) all parameters are measured with no output loads. 4) value shown as typical. parameter & test conditions max. temperature symbol values units notes 1)2) typ. max. self refresh current: self refresh mode, full array activation(pasr = 000) 85 c i dd6 1020 1200 a? 70 c680? 45 c 450 ? 25 c 410 ? self refresh current: self refresh mode, half array activation(pasr = 001) 85 c800940 70 c 530 ? 45 c 400 ? 25 c 360 ? parameter & test conditio ns symbol valuea unit notes 1) - 7.5
data sheet. rev. 1.22, 2006-12 51 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 3.4 pullup and pulldown characteristics table 29 half drive strength (default) and full drive strength the above characteristics are specified under nomi nal process variation / conditiontemperature ( t j ): nominal = 50 c, v ddq : nominal = 1.80 v self refresh current: self refresh mode, quarter array activation(pasr = 010) 85 c i dd6 680 800 a? 70 c 500 ? 45 c 370 ? 25 c 340 ? 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = v ddq = 1.70 v to 1.95 v 2) the on-chip temperature sensor (octs) adjusts the refresh rate in self refresh mode to the component?s actual temperature wit h a much finer resolution that supported by the 4 distinct temperature le vels as defined by jedec for tc sr. at production test, the sens or is calibrated, and idd6 max. current is measured at 85c. typ. values are obtained from device characterization. voltag e (v) half drive strength (default) full drive strength pull-down current (ma) pull-up current (ma) pull-down current (ma) pull-up current (ma) nominal low nominal high nominal low nominal high nominal low nominal high nominal low nominal high 0.00 0.0 0.0 -19.7 -33.4 0.0 0.0 -39.3 -66.7 0.40 15.1 20.5 -18.8 -32.0 30.2 41.0 -37.6 -63.9 0.65 20.3 28.5 -18.2 -31.0 40.5 57.0 -36.4 -61.9 0.85 22.0 32.0 -17.6 -29.9 43.9 64.0 -35.1 -59.8 1.00 22.6 33.5 -16.7 -28.7 45.2 67.0 -33.3 -57.3 1.40 23.5 35.0 -9.4 -20.4 46.9 70.0 -18.8 -40.7 1.50 23.6 35.3 -6.6 -17.1 47.2 70.5 -13.2 -34.1 1.65 23.8 35.5 -1.8 -11.4 47.5 71.0 -3.5 -22.7 1.80 23.9 35.7 3.8 -4.8 47.7 71.4 7.5 -9.6 1.95 24.0 35.9 9.8 2.5 48.0 71.8 19.6 5.0 parameter & test conditions max. temperature symbol values units notes 1)2) typ. max.
data sheet. rev. 1.22, 2006-12 52 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 4 package outlines figure 48 pg-tfbga-54 (plastic green - thin fine ball grid array package) 0 ? 0 , 1 0 $; $ 0 d u n l q j % d o o v l g h % d g 8 q l w 0 d u n l q j % 8 0 0 l g g o h r i 3 d f n d j h v ( g j h v ? 0 $; ? $ ? [ 0 & * 3 $ 6 ( $7, 1 * 3 /$1 ( [ $ % & % & 0 $; [ & &
data sheet. rev. 1.22, 2006-12 53 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram figure 1 standard ballout 512-mbit mobile-ram 5 figure 2 functional block diagram 6 figure 3 power-up sequence and mode register sets 8 figure 4 state diagram 14 figure 5 address / command inputs timing parameters 16 figure 6 no operation command 17 figure 7 mode register set command 17 figure 8 mode register definition 18 figure 9 active command 18 figure 10 bank activate timings 19 figure 11 read command 20 figure 12 basic read timing parameters for dqs 20 figure 13 single read burst (cas latency = 2) 21 figure 14 single read burst (cas latency = 3) 22 figure 15 consecutive read bursts 22 figure 16 random read bursts 23 figure 17 non-consecutive read bursts 23 figure 18 terminating a read burst 24 figure 19 clock suspend mode for read bursts 25 figure 20 read burst - dqm operation 25 figure 21 read to write timing 26 figure 22 read to precharge timing 27 figure 23 write command 28 figure 24 basic write timing pa rameters for dqs 28 figure 25 list of figures
data sheet. rev. 1.22, 2006-12 54 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram write burst (cas latency = 2) 29 figure 26 write burst (cas latency = 3) 30 figure 27 consecutive write bursts 30 figure 28 random write bursts 31 figure 29 non-consecutive write bursts 31 figure 30 terminating a write burst 32 figure 31 clock suspend mode for write bursts 33 figure 32 write burst - dqm operation 33 figure 33 write to read timing 34 figure 34 write to precharge timing 35 figure 35 burst terminate command 35 figure 36 precharge command 36 figure 37 read with auto precharge interrupted by read 37 figure 38 read with auto precharge interrupted by write 38 figure 39 write with auto precharge interrupted by read 38 figure 40 write with auto precharge interrupted by write 39 figure 41 auto refresh command 39 figure 42 auto refresh 40 figure 43 self refresh entry command 40 figure 44 self refresh entry and exit 41 figure 45 power down entry command 42 figure 46 power down entry and exit 42 figure 47 49 figure 48 pg-tfbga-54 (plastic green - thin fine ball grid array package) 52
data sheet. rev. 1.22, 2006-12 55 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 pin definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1.4 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1.5 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1.6 partial array self refr esh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1.7 temperature compensated self refresh (tcsr) with on-chip temperature sensor . . . . . . . . . . . . . . . . . 13 2.2.1.8 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.1 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.3 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.4 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.5 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.5.1 read burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.5.2 clock suspend mode for read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.5.3 read - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.5.4 read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.5.5 read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.6 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.6.1 write burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.6.2 clock suspend mode for write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.6.3 write - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.6.4 write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.6.5 write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.7 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.8 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.8.1 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.8.2 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.9 auto refresh and self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.9.1 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.9.2 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.10 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.10.1 deep power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5 function truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents
data sheet. rev. 1.22, 2006-12 56 01132005-06iu-igvm hy[b/e]18l512160bf-7.5 512-mbit mobile-ram 3.4 pullup and pulldown characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
edition 2006-12 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2006. all rights reserved. legal disclaimer the information given in this data sheet shall in no event be regarded as a guarantee of co nditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. under no circumstances may the qimonda product as referred to in this data sheet be used in 1. any applications that are intended for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices an d systems collectively referred to as "critical systems"), if a) a failure of the qimonda product can reasonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reliability, effectiveness or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such critical systems ca n reasonably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not lim ited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com data sheet.

▲Up To Search▲

Price & Availability of HYB18L512160BF-75

	To Download HYB18L512160BF-75 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .